Computer programs are typically written in a high level language, such as "C", Fortran, Pascal, Basic, etc., which has more readily accessible meaning to the original programmer (or to another seeking to understand the program structure) than does a listing of a sequence of machine level instructions. The program expressed in the high level language is known as "source code". However, source code will not execute directly and therefore must either be interpreted, statement by statement, into executable code as a program is run or first compiled into "object code" (which is meaningful on the given hardware employing the given operating system) and then run as object code. The compilation is performed by a special purpose "compiler" program which has an awareness of the architecture: of the computer system with which the object code will be used and can therefore translate each source code statement into one or more system specific object code instructions. Those skilled in the art will understand that executing compiled object code is very much faster than executing source code through an interpreter, and most commercial code is provided only in compiled form.
As faster operation of computers has been sought, numerous hardware/firmware features have been employed to achieve that purpose. One widely incorporated feature directed to increasing the speed of operation is pipelining in which the various stages of execution of a series of consecutive machine level instructions are undertaken simultaneously. Thus, during a given time increment, a first stage of a fourth (in order of execution) instruction may be undertaken while a second stage of a third instruction, a third stage of a second instruction and a fourth stage of a first instruction are all undertaken simultaneously.
This procedure dramatically increases the apparent speed of operation of a computer system. However, there are instances in which conflicts arise among the sequential instructions which can bring about a pipeline "break", i.e., a need to interrupt the smooth interleave of the succeeding instructions in order to wait out the conflict. As an elementary example, if, in undertaking the first stage of a fourth instruction, a given register is used for an operand address and the same register is simultaneously being altered by undertaking the second stage of the third instruction, a conflict exists, and the first stage of the fourth instruction must be postponed, thereby resulting in a pipeline break and a consequent decrease in the apparent speed of execution. The present invention directly addresses, and serves to minimize, the problem of software breaks in compiled object code employed in a computer processor employing pipelined architecture.